Abstract
An 2.5D IC could be composed of a number of functional dies operating in locked steps defined by a global clock signal. However, the clock network design across multiple dies may not be trivial as the die-to-die interconnects used for relaying the clock signal from a source die to the other receiver dies could be unpredictable in their delays in real silicon. In this work, we propose a characterization-and-tuning procedure for die-to-die clock skew minimization. Experimental results show that a die-to-die clock skew of 98.3ps due to the differences of process corners can be thereby reduced to only 26.1ps.