Digit-serial VLSI architecture for delayed LMS adaptive FIR filtering

Chin-Liang Wang; Ching-Chia Chen; Che-Fu Chang

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Digit-serial VLSI architecture for delayed LMS adaptive FIR filtering

Chin-Liang Wang, Ching-Chia Chen and Che-Fu Chang

Proceedings - IEEE International Symposium on Circuits and Systems, Vol.1, pp.545-548

1995

Abstract

In this paper, we present a digit-serial VLSI architecture for realization of an adaptive FIR filter equipped with the delayed least mean square (LMS) algorithm. The architecture is attractive for use in applications where bit-serial arithmetic is too slow and bit-parallel arithmetic requires too much hardware or cannot reach the desired convergence performance.

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Title: Digit-serial VLSI architecture for delayed LMS adaptive FIR filtering
Creators - without role: Chin-Liang Wang - Natl Tsing Hua Univ
Ching-Chia Chen - Natl Tsing Hua Univ
Che-Fu Chang - Natl Tsing Hua Univ
Publication Details: Proceedings - IEEE International Symposium on Circuits and Systems, Vol.1, pp.545-548
Grant note: IEEE
Identifiers: 9957768266406774
Academic Unit: Institute of Communications Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

Digit-serial VLSI architecture for delayed LMS adaptive FIR filtering

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