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Dynamic Performance Enhancement of Single-Phase and Two-Phase Enhanced Phase-Locked Loops by Using In-Loop Multiple Delayed Signal Cancellation Filters
Conference paper   Peer reviewed

Dynamic Performance Enhancement of Single-Phase and Two-Phase Enhanced Phase-Locked Loops by Using In-Loop Multiple Delayed Signal Cancellation Filters

Srinivas Gude and Chia-Chi Chu
IEEE Transactions on Industry Applications, Vol.56(1), pp.740-751
01/2020

Abstract

Amplitude enhanced phase-locked loops (EPLLs) frequency multiple delayed signal cancellation (MDSC) phase angle PI controller PID controller Control and Systems Engineering Industrial and Manufacturing Engineering Electrical and Electronic Engineering
The estimation of phase-angle, frequency, and amplitude are vital for the control of grid-connected power electronic systems in both single-phase and three-phase systems. The single-phase enhanced phase-locked loop (1P-EPLL) and two-phase enhanced phase-locked loop (2P-EPLL) techniques can be used to estimate single-phase and three-phase grid voltage quantities, respectively. However, under the presence of harmonics, unbalance, and dc offsets, the estimated quantities by these enhanced phase-locked loops (EPLLs) may contain periodic ripples. These periodic ripples are eliminated by using multiple delayed signal cancellation (MDSC) filters in the phase-angle estimation loop and amplitude estimation loop of these EPLLs. To improve the dynamic responses of MDSC-based EPLLs, proportional-integral (PI) controller is replaced with a proportional-integral-derivative (PID) controller. The design guidelines for choosing the control parameters are provided. The MDSC filters in the EPLLs are realized both in direct-form and recursive-form structures. The proposed EPLLs are verified experimentally by using real-time system and compared with recent advanced EPLLs.

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