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EC-Cache: Exploiting error locality to optimize ldpc in NAND flash-based SSDS
Conference paper

EC-Cache: Exploiting error locality to optimize ldpc in NAND flash-based SSDS

Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho and Hsiang-Pang Li
Proceedings - Design Automation Conference, 2593130
2014

Abstract

Bit errors Cache LDPC NAND flash SSD
Low-density parity-check (LDPC) is widely accepted as the baseline error-correction codes offering strong error-correcting capability for future NAND flash-based SSDs. However, LDPC incurs read performance overhead because of its complex decoding procedure. To mitigate such overhead, we propose the error-correcting cache (EC-Cache) that exploits the ""error locality"" of NAND flash. Error locality means that the majority of errors in reads to the same NAND flash page appear in the same positions until the page is erased. By caching detected errors, EC-Cache can correct a significant portion of errors present in a requested flash page before the associated LDPC decoding process begins. EC-Cache can greatly speed up LDPC decoding because LDPC's latency is directly correlated to the number of errors present in the input data. Experimental results show that EC-Cache achieves up to 2.6× SSD read performance gain. Copyright 2014 ACM.

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