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Edge-extended design for improved flicker noise characteristics in 0.13-μm RF NMOS
Conference paper

Edge-extended design for improved flicker noise characteristics in 0.13-μm RF NMOS

Chih-Yuan Chan, Yu-Syuaii Lin, Yen-Chun Huang, Shawn S. H. Hsu and Ying-Zong Juang
IEEE MTT-S International Microwave Symposium Digest, pp.441-444
2007

Abstract

Flicker noise RF CMOS Shallow trench isolation (SIT)
This paper proposed a new device layout to improve the flicker noise and generation-recombination (G-R) noise characteristics in 0.13-μm RF N-MOSFETs. By extending the active region edge along the gate, the impact of stress and traps introduced by shallow trench isolation (STI) on device flicker noise was reduced significantly. Under a fixed V DS of 1 V and V GS of 0.5 V, the edge-extended devices (W/L= 1/0.13, N finger = 40) present a reduced noise current spectral density (S ID /I 2 ) variation to only ∼ one third (S ID /I 2 ) ranges from 4.5×10 -12 to 9.4×10 -12 Hz -1 at 100 Hz) of that for devices with conventional layout (S ID /I 2 ranges from 2.33×10 -12 to 1.69×10 -11 Hz -1 at 100 Hz). The associated G-R bulges in flicker noise were almost disappeared with the new design. This study indicates the imperfections and stress at the STI edge are important origins to affect flicker noise characteristics especially for RF devices with a small finger width. In addition, the tradeoff between the improved flicker noise characteristics and the device RF performance is also investigated. © 2007 IEEE.

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