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Effects of array type of dummy active diffused region and gate geometries on narrow NMOSFETs with SiC S/D stressors
Conference paper

Effects of array type of dummy active diffused region and gate geometries on narrow NMOSFETs with SiC S/D stressors

Chang-Chun Lee, Chia-Ping Hsieh, Ming-Han Liao, Sen-Wen Cheng and Yu-Huan Guo
2014 IEEE International Nanoelectronics Conference, INEC 2014, 7460419
04/2016
DOI: https://doi.org/10.1109/INEC.2014.7460419

Abstract

Lattice-mismatch strained engineering Layout pattern effect Mobility gain estimation SiC stressor Stress simulation Electrical and Electronic Engineering
To investigate the combined strained effects of dummy active diffused region (OD) and salient gate width of layout pattern on the mobility gain of nano-scaled device while advanced stressors of source/drain embedded silicon-carbon alloy and a tensile contact etch stop layers (CESL) are taken into account, the study uses a validated fabricated-oriented stress simulated methodology to estimate the performance of a 22nm NMOSFET.

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