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Effects of pressure and bias voltage on the phase noise of CMOS-MEMS oscillators
Conference paper

Effects of pressure and bias voltage on the phase noise of CMOS-MEMS oscillators

Wan-Cheng Chiu, Ming-Huang Li, Chao-Yu Chen and Sheng-Shian Li
2015 Joint Conference of the IEEE International Frequency Control Symposium and the European Frequency and Time Forum, FCS 2015 - Proceedings, pp.155-157
29/06/2015

Abstract

CMOS MEMS monolithic integration oscillators phase noise resonators sustaining circuits Computer Networks and Communications,Signal Processing
In this work, we present a comprehensive study on the effects of environmental pressure (P) and resonator dc-bias voltage for the phase noise of a monolithic CMOS-MEMS oscillator. In order to access the practical utility of CMOS-MEMS oscillators for versatile applications, a double-ended tuning fork (DETF) MEMS resonator oscillator is used as a case study. In the ambient pressure, the oscillation ensues at a minimum V <sub>P</sub> = 30V and shows a phase noise (PN) of -86 dBc/Hz at 1-kHz offset and -99 dBc/Hz at 1-MHz offset. On the other hand, a low-V <sub>P</sub> CMOS-MEMS oscillator with IC compatible voltage (i.e., V <sub>P</sub> = 3V, leading to an equivalent motional impedance R <sub>m</sub> of 100 Mω) is also demonstrated in a vacuum chamber (P < 1 mTorr) with a PN of -94 dBc/Hz at 1-kHz offset and -98 dBc/Hz at 1-MHz offset, respectively.

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