Efficient 2-D systolic array implementation of a prime factor DFT algorithm

C.-L. Wang; Y.-T. Chang

doi:10.1109/TENCON.1992.271984

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Conference paper

Efficient 2-D systolic array implementation of a prime factor DFT algorithm

C.-L. Wang and Y.-T. Chang

IEEE Region 10 Annual International Conference, Proceedings/TENCON, pp.56-60

1992

DOI: https://doi.org/10.1109/TENCON.1992.271984

Abstract

Computer Science Applications

Electrical and Electronic Engineering

A new two-dimensional systolic array for computing the discrete Fourier transform (DFT), with length N decomposable into the product of two relatively prime factors, 4M ₁ and M ₂ , is presented. The architecture is constructed based on the row-column algorithm. It does not include any intermediate circuit for arranging data flow between the row-DFT and column-DFT modules. The system possesses the features of regularity and modularity, and is well suited to VLSI implementation. It has an efficiency of 100%, a throughput rate of one N-point transform per M ₂ cycles, and an areatime ² figure of AT ² =O((M ₁ +M ₂ )M ₂ N log ₂ ² N), which is much smaller than the value of O(N ³ log ₂ ² N) achieved by existing linear systolic array solutions.

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Title: Efficient 2-D systolic array implementation of a prime factor DFT algorithm
Translated title: Efficient 2-D systolic array implementation of a prime factor DFT algorithm
Creators - without role: C.-L. Wang - National Tsing Hua University
Y.-T. Chang - National Tsing Hua University
Identifiers: 0780308492; 9957772346206774
Academic Unit: Institute of Communications Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper
Publication Details: IEEE Region 10 Annual International Conference, Proceedings/TENCON, pp.56-60

Efficient 2-D systolic array implementation of a prime factor DFT algorithm

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