Abstract
Fault diagnosis that analyzes the most likely defect locations in a defective chip is an important step for manufacturing yield improvement or design debugging. In this paper, we address the double fault diagnosis for fullscandesigns. The features of our algorithm include the following. (1) We propose an effective selection heuristic to avoid the candidate space explosion problem, while retaining a high success rate of catching both faults. (2)We apply a ranking heuristic to further achieve a high accuracy, in a sense that the fault can be identified quickly.Experimental results on ISCAS85 benchmark circuits injected with a random bridging fault, two stuck-at faults, or two gate-type faults show that both faults can be caught simultaneously within several minutes with a high success rate.