Efficient Segment-wise Pruning for DCNN Inference Accelerators

Che-Chang Yang; Yung-Tai Shih; Chun-Chen Chen; Chih-Tsun Huang; Jing-Jia Liou; Yao-Hua Chen; Juin-Ming Lu

doi:10.1109/VLSI-DAT54769.2022.9768076

會議論文

Efficient Segment-wise Pruning for DCNN Inference Accelerators

Che-Chang Yang, Yung-Tai Shih, Chun-Chen Chen, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen 和 Juin-Ming Lu

Proceedings of Technical Program of International Symposium on VLSI Design, Automation and Test, 頁碼.1-4

IEEE

2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (Hsinchu, Taiwan, 18/04/2022–21/04/2022)

18/04/2022

DOI: https://doi.org/10.1109/VLSI-DAT54769.2022.9768076

摘要

Accelerator architectures

Analytical models

Design automation

Indexes

Very large scale integration

Energy Consumption

Space Exploration

This paper presents a structure pruning with design space exploration for DCNN accelerators. The design space exploration tool, called NNArch, generates optimized design scheduling for the row-stationary DCNN accelerators with fast and accurate analytical performance/energy models. Based on the NNArch, the proposed filter-segment pruning can efficiently compress the DCNNs with a simple filter index table, optimizing model accuracy, accelerator performance, and energy consumption. The experiment result shows that the proposed pruning scheme can achieve 2 times speedup and improve the energy-delay-product by 3.42 times on ResNet50 with the accuracy drop of 0.2%, on the accelerator of 168 PEs.

指標

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詳細資料

題名: Efficient Segment-wise Pruning for DCNN Inference Accelerators
創作者：: Che-Chang Yang - National Tsing Hua University
Yung-Tai Shih - National Tsing Hua University
Chun-Chen Chen - National Tsing Hua University,Department of Computer Science,Hsinchu,Taiwan
Chih-Tsun Huang - 國立清華大學, 半導體研究學院
Jing-Jia Liou - 國立清華大學, 半導體研究學院
Yao-Hua Chen - Industrial Technology Research Institute,Electronic & Optoelectronic System Research Laboratories,Hsinchu,Taiwan
Juin-Ming Lu - National Tsing Hua University,Department of Electrical Engineering,Hsinchu,Taiwan
會議: 2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (Hsinchu, Taiwan, 18/04/2022–21/04/2022)
出版者: IEEE
總頁數: 4
補助款備註: MOST 110-2218-E-007-041,MOST 110-2622-8-007-018 / Ministry of Science and Technology, Taiwan ROC (10.13039/501100004663)
學術資源類型: 會議論文
出版日期: 18/04/2022
出版資訊: Proceedings of Technical Program of International Symposium on VLSI Design, Automation and Test, 頁碼.1-4
語言: 英語

Efficient Segment-wise Pruning for DCNN Inference Accelerators

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指標

詳細資料

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