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Efficient neighborhood pattern-sensitive fault test algorithms for semiconductor memories
Conference paper

Efficient neighborhood pattern-sensitive fault test algorithms for semiconductor memories

K.-L. Cheng, M.-F. Tsai and C.-W. Wu
Proceedings of the IEEE VLSI Test Symposium, pp.225-230
2001

Abstract

Computer Science Applications Electrical and Electronic Engineering
We present two memory test algorithms for neighborhood pattern sensitive faults (NPSFs), including Static NPSF (SNPSF), passive NPSF (PNPSF) and active NPSF (ANPSF). March algorithms are widely used in memory testing because of their linear time complexity and ease in built-in self-test (BIST) implementation. Although conventional March algorithms do not generate all neighborhood patterns for testing the NPSFs, they can be modified by using multiple data backgrounds such that all neighborhood patterns can be generated. The proposed multi-background March algorithms have shorter test length than previously proposed ones (68N for detecting SNPSFs and PNPSFs and 96N for detecting all NPSFs). Also, based on the proposed algorithms, linear-time BIST circuit can be implemented with low area overhead.

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