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Enabling Low Power BEOL Compatible monolithic 3D+ nanoelectronics for IoTs Using Local and Selective Far-Infrared Ray Laser Anneal Technology
Conference paper

Enabling Low Power BEOL Compatible monolithic 3D+ nanoelectronics for IoTs Using Local and Selective Far-Infrared Ray Laser Anneal Technology

Chih-Chao Yang, Jia-Min Shieh, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, 昌宏 沈, Tsung-Ta Wu, Tsung-Ta Wu, Yun-Fang Hou, Yi-Ju Chen, …
2015 IEEE International Electron Devices Meeting (IEDM)
12/2015
DOI: https://doi.org/10.1109/IEDM.2015.7409657

Abstract

Silicon;Annealing;Resistance;Three-dimensional displays;Field effect transistors;Nanoelectronics;Logic gates

Local and selective far-infrared ray laser annealing (FIR-LA) process with very short heating duration (<;100μs) and low substrate temperature (<;400°C) enables sequentially stacked gate-first nanowire FETs (NWFETs), including 3D+ Si NWFET and poly-Ge junctionless (JL) NWFET, and BEOL compatible monolithic 3D+ nanoelectronics. The 3D+ Si NWFETs, demonstrated by green nano-second laser crystallization (GNS-LC) and FIR-LA processes exhibit steep subthreshold swing (<;90mV/dec.) and high driving current (n-type: 310μA/μm and p-type: 220μA/μm). The 7nm poly-Ge JLNWFET shows high Ion/Ioff ratio (>5×104) and small DIBL. Furthermore, the thus fabricated low driving voltage 6T SRAM shows a static noise margin (SNM) of 130 mV at Vd=0.4V enabling the low power and low cost 3D+IC for internet of things (IoTs).

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