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Enhancing Solver Robustness through Constraint Tightening for DNN Compilation
會議論文

Enhancing Solver Robustness through Constraint Tightening for DNN Compilation

Chia-Wei Chang 和 Jing-Jia Liou
2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), 頁碼.1-4
IEEE
2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA) (HsinChu, Taiwan, 22/04/2024–24/04/2024)
22/04/2024
Web of Science ID: WOS:001253001400110

摘要

Constraint Tightening Distance measurement DNN Compiler Hardware Optimizer Robustness Solver Robustness Very large scale integration Engines Optimization
DNN compilers play a crucial role in mapping the loop nest onto accelerators. While existing approaches efficiently optimize these loop nests through multilevel optimization coupled with a convex solver, some case studies reveal a low robustness in handling data reuse across multiple NoC-interconnected engines. This issue is caused from hardware constraint violations during multilevel optimization. To address this challenge and enhance the robustness of the optimizer, this paper introduces a constraint tightening technique. The proposed technique achieves 100% solvability on end-to-end DNN optimization. With high solvability, especially on fused DNN layers, constraint tightening demonstrates a 1.14x EDP improvement.

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