Evaluation of Redundancy Analysis Schemes for Reparable Memories with Redundancy Constraints

Conference paper

C.-H. Lin, M.-S. Lee, C.-L. Su and C.-W. Wu

Proc. 2nd VLSI Test Technology Workshop (VTTW)

2008

Abstract

Redundancy Analysis Schemes;Redundancy Constraints

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Title: Evaluation of Redundancy Analysis Schemes for Reparable Memories with Redundancy Constraints
Creators - without role: C.-H. Lin
M.-S. Lee
C.-L. Su
C.-W. Wu - 國立清華大學電機資訊學院電機工程學系
Publication Details: Proc. 2nd VLSI Test Technology Workshop (VTTW)
Identifiers: 9957767353306774
Academic Unit: College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: Traditional Chinese
Resource Type: Conference paper