摘要
There are several applications of functional simulation with transient faults including evaluation of the vulnerability and design error-tolerant measures, as well as debugging of electrical hardware issues. Yet, the simulation is extremely slow given the complexity of RTL circuits and a large number of transient faults proportional to the total execution cycles. Recently, fault reduction methods are developed with Architecturally Correct Execution (ACE) analysis. The method can identify only about 3 % of total faults deemed necessary for simulation. However, the analysis effort is still non-trivial and most of the time is consumed in the small single-cycle fault simulation. In this paper, we proposed to use FPGA emulation to speedup the above process. In the experiments, on a RISC- V core, for a set of 16K faults, the analysis time are reduced from 1 hours to 1min, On average, the fault emulation has a speed up factor of 60 compared with a software implementation.