Failure mechanism of high-voltage isolated lateral diffused NMOS under high-current events

Cheng-Hsu Wu; Chen-Hsin Lien; Jian-Hsing Lee

doi:10.1109/IRPS.2016.7574603

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Conference paper

Failure mechanism of high-voltage isolated lateral diffused NMOS under high-current events

Cheng-Hsu Wu, Chen-Hsin Lien and Jian-Hsing Lee

IEEE International Reliability Physics Symposium Proceedings, Vol.2016-September, pp.EL21-EL25

09/2016

DOI: https://doi.org/10.1109/IRPS.2016.7574603

Appears in keyword about Physics

Abstract

Deeply depleted

Electrostatic discharge

Secondary breakdown current

Snapback

Trigger voltage

Engineering (all)

In this study, the mechanism of the effect of a high-voltage (HV) NWell guardring (NW-GR) on the electrostatic discharge (ESD) robustness of the HV isolated lateral diffused NMOS (HV ISO-LDNMOS) is investigated. The device fails on low-voltage ESD zapping events when the HVNW-GR is connected to the drain, whereas the device passes these events once it is floated.

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Title: Failure mechanism of high-voltage isolated lateral diffused NMOS under high-current events
Creators - without role: Cheng-Hsu Wu - National Tsing Hua University
Chen-Hsin Lien - Institute of Electronics Engineering , National Tsing Hua University
Jian-Hsing Lee - Reliability Engineering Department , Global Foundries Inc.
Publication Details: IEEE International Reliability Physics Symposium Proceedings, Vol.2016-September, pp.EL21-EL25
Identifiers: 9781467391368; 9957770716406774
Academic Unit: College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

Failure mechanism of high-voltage isolated lateral diffused NMOS under high-current events

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