False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

Jing-Jia Liou; Angela Krstic; Li-C. Wang; Kwang-Ting Cheng

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Conference paper

False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

Jing-Jia Liou, Angela Krstic, Li-C. Wang and Kwang-Ting Cheng

Proceedings - Design Automation Conference, pp.566-569

2002

Abstract

Critical path selection

False path

Statistical timing analysis

We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths.

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Title: False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
Creators - without role: Jing-Jia Liou - Elec. and Computer Engineering Dept. , University of California
Angela Krstic - Elec. and Computer Engineering Dept. , University of California
Li-C. Wang - Elec. and Computer Engineering Dept. , University of California
Kwang-Ting Cheng - Elec. and Computer Engineering Dept. , University of California
Grant note: IEEE
Identifiers: 1581134614; 9957772984306774
Academic Unit: Department of Electrical Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper
Publication Details: Proceedings - Design Automation Conference, pp.566-569

False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

Abstract

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