摘要
The rapid growth of artificial intelligence (AI) applications has driven increasing demand for diverse, small-volume, and fast-turnaround chip development. To address these needs, this work proposes a cost-effective shuttle service platform based on a mask-sharing strategy, enabling rapid prototyping and small-lot manufacturing for advanced packaging technologies. A multilayer redistribution layer (RDL) process was developed using an RDL-first fan-out approach on a 12-inch glass carrier. The fabricated structure consists of six copper metal layers (6M) with a minimum line width of 5 μm and five polyimide passivation layers (5P), including four intermediate routing layers. Process optimization, layout density balancing, and coefficient of thermal expansion (CTE) compensation were implemented to suppress wafer warpage, achieving close agreement between simulation and measurement. Electrical characterization demonstrated yields exceeding 90%, picoampere-level leakage currents, and robust Cu/PI interfacial adhesion. The results confirm that the proposed shuttle service platform is well suited for agile, small-volume AI chip development and advanced heterogeneous integration.