Fault Models and Test Algorithms for Multi-Level Cell (MLC) Crossbar RRAM

Conference paper

Fault Models and Test Algorithms for Multi-Level Cell (MLC) Crossbar RRAM

K.-W. Hou and C.-W. Wu

Proc. VLSI Test Technology Workshop (VTTW)

07/2017

Abstract

Fault;Test Algorithm;Multi-Level Cell (MLC);Crossbar;RRAM

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Title: Fault Models and Test Algorithms for Multi-Level Cell (MLC) Crossbar RRAM
Creators - without role: K.-W. Hou
C.-W. Wu
Publication Details: Proc. VLSI Test Technology Workshop (VTTW)
Identifiers: 9957776183206774
Academic Unit: College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: Traditional Chinese
Resource Type: Conference paper