Fault equivalence analysis and reduction of two level test set for multilevel logic synthesis

Wen-Jun Hsu; Wen-Zen Shen; Jyuo-Min Shyu

doi:10.1109/ISCAS.1992.229925

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Conference paper

Fault equivalence analysis and reduction of two level test set for multilevel logic synthesis

Wen-Jun Hsu, Wen-Zen Shen and Jyuo-Min Shyu

Proceedings - IEEE International Symposium on Circuits and Systems, Vol.1, pp.415-418

1992

DOI: https://doi.org/10.1109/ISCAS.1992.229925

Abstract

Electrical and Electronic Engineering

In this paper, we analyze the relation of faults between synthesized multilevel network and its collapsed two-level network. With the analysis, we also implement a program to select a proper set of faults in collapsed twolevel network from the synthesized mutilevel network. The tests for selected faults will detect all single stuck-at faults of the synthesized multilevel network. The number of generated tests is about 50% less than the number of twolevel complete test set.

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Title: Fault equivalence analysis and reduction of two level test set for multilevel logic synthesis
Translated title: Fault equivalence analysis and reduction of two level test set for multilevel logic synthesis
Creators - without role: Wen-Jun Hsu - National Yang Ming Chiao Tung University
Wen-Zen Shen - National Yang Ming Chiao Tung University
Jyuo-Min Shyu - Industrial Technology Research Institute
Publication Details: Proceedings - IEEE International Symposium on Circuits and Systems, Vol.1, pp.415-418
Identifiers: 0780305930; 9957767052606774
Academic Unit: National Tsing Hua University
Language: English
Resource Type: Conference paper

Fault equivalence analysis and reduction of two level test set for multilevel logic synthesis

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