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FinFET-based Monolithic 3D+ with RRAM array and computing in memory SRAM for intelligent IoT chip application
Conference paper

FinFET-based Monolithic 3D+ with RRAM array and computing in memory SRAM for intelligent IoT chip application

Kai-Shin Li, Fu-Kuo Hsueh, Jia-Min Shieh, Hsiu-Chih Chen, Wen-Hsien Huang, Hsiao-Yun Chiu, Chih-Chao Yang, Tung-Ying Hsieh, Bo-Yuan Chen, Wei-Hao Chen, …
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, 8640186
02/2019
DOI: https://doi.org/10.1109/S3S.2018.8640186

Abstract

Hardware and Architecture Electrical and Electronic Engineering Safety Risk Reliability and Quality Electronic Optical and Magnetic Materials Instrumentation
We report heterogeneously integrated sub-40nm epi-like monolithic 3DIC with vertical ReRAM and memory computing (NMC) circuit. High driving current multi-channel UTB-MOSFETs (3.3/1.4 mA μ m for N/P FETs) was realized by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO <sub>2</sub> far-infrared laser annealing (CO <sub>2</sub> -FIR-LA) activation technologies that enable driving 20nm 4-layer vertical ReRAM (Set/Reset < 1.2 V/1.8V, 3-bits/cell). Furthermore, the ultra-low threshold voltage of NC-FinFETs and the differential output of SRAM readout enable 50 +% area reduction in the near-memory computing circuitry. The unique TSV-free monolithic 3D <sup>+</sup> IC process provides the superiority in 3D hetero-integration to realize low cost, small footprint, fully functionalized 3D IoTs chip.

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