Abstract
In this paper, we propose a fine-grain approach for enhancing the accuracy of the mixed-level power estimation. It was shown previously that there often exists a statistical correlation between the steady-state transition power and the hazardous power (including the glitching power and short-circuit power) in a CMOS logic circuit. The accuracy of mixed-level power estimation strongly relies on accurate modeling of this correlation. Based on this observation, we propose to partition the logic gates into groups based on so-called disparity path analysis. Then, one correlation factor is calculated to characterize the power dissipation behavior of each group. Experimental results show that such a fine-grain technique can further reduce the estimation error to less than 1% as compared to the results of PowerMill under normal functional patterns.