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Fine-grained sleep transistor sizing algorithm for leakage power minimization
Conference paper   Open access

Fine-grained sleep transistor sizing algorithm for leakage power minimization

De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen and Shih-Chieh Chang
Proceedings - Design Automation Conference, pp.81-86
2007

Abstract

IR drop Leakage current Power gating
Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep transistor networks from a temporal viewpoint. Based on this relationship, we propose an algorithm to reduce the total sizes of sleep transistors in Distributed Sleep Transistor Network designs. On average, the proposed method can achieve 21% reduction in the sleep transistor size. Copyright 2007 ACM.
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https://doi.org/10.1109/DAC.2007.375129View
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