Logo image
Back
GaN cascode performance optimization for high efficient power applications
Conference paper

GaN cascode performance optimization for high efficient power applications

Haw-Yun Wu, Ming-Cheng Lin, Nan-Ying Yang, C.T. Tsai, C.B. Wu, Y.S. Lin, Y.C. Chang, P.C. Chen, K.Y. Wong, M.H. Kwan, …
Proceedings of the International Symposium on Power Semiconductor Devices and ICs, Vol.2016-July, pp.255-258
07/2016
DOI: https://doi.org/10.1109/ISPSD.2016.7520826

Abstract

Engineering (all)
GaN Cascode performance optimization for high efficient power applications is presented in this paper. Analytical equations of Cascode capacitance network (Ciss, Coss, Cgd) is demonstrated and the equations accuracy is verified through experimental measurement. Analysis shows that Cascode Cgd is determined by HV D-MISFETs Cds, LV Si FETs Cgd/Coss ratio, and extra zener diode capacitance. With low intrinsic capacitance HV D-MISFETs [1-2], proper LV Si FETs selection, and extra zener diode protection, optimization for Cascode switching figure-of-merit (FOM, Ron x Qgd) is well demonstrated. 8.8X lower switching figure-of-merit than commercial best-in-class Si SJ FETs [3] is achieved, double pulse test (DPT) and hard switching PFC system verification result all indicate that GaN Cascode is the promising solution and ready for next generation energy systems.

Metrics

1 Record Views

Details

Logo image