Gate-Delay Fault Diagnosis Using The Inject-And-Evaluate Paradigm For Full-Scan Designs

Conference paper

H.-B. Wang, S.-Y. Huang and J.-R. Huang

Proc. of Int'l Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'02)

2002

Abstract

Gate-Delay Fault Diagnosis;Inject-And-Evaluate Paradigm;Full-Scan Designs

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Title: Gate-Delay Fault Diagnosis Using The Inject-And-Evaluate Paradigm For Full-Scan Designs
Creators - without role: H.-B. Wang
S.-Y. Huang - 國立清華大學電機資訊學院電機工程學系
J.-R. Huang
Publication Details: Proc. of Int'l Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'02)
Identifiers: 9957768383606774
Academic Unit: Department of Electrical Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: Traditional Chinese
Resource Type: Conference paper