Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

C.-J. Su; T.-C. Hong; Y.-C. Tsou; F.-J. Hou; P.-J. Sung; M.-S. Yeh; C.-C. Wan; K.-H. Kao; Y.-T. Tang; C.-H. Chiu; C.-J. Wang; S.-T. Chung; T.-Y. You; Y.-C. Huang; C.-T. Wu; K.-L. Lin; G.-L. Luo; K.-P. Huang; Y.-J. Lee; T.-S. Chao; W.-F. Wu; G.-W. Huang; J.-M. Shieh; W.-K. Yeh; Y.-H. Wang

doi:10.1109/IEDM.2017.8268396

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Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

C.-J. Su, T.-C. Hong, Y.-C. Tsou, F.-J. Hou, P.-J. Sung, M.-S. Yeh, C.-C. Wan, K.-H. Kao, Y.-T. Tang, C.-H. Chiu, …

Technical Digest - International Electron Devices Meeting, IEDM, pp.15.4.1-15.4.4

01/2018

DOI: https://doi.org/10.1109/IEDM.2017.8268396

Appears in keyword about Physics

Abstract

Electronic

Optical and Magnetic Materials

Condensed Matter Physics

Electrical and Electronic Engineering

Materials Chemistry

Ge nanowire (NW) FETs exhibiting subthreshold swing (SS) of 54 mV/dec at room temperature are demonstrated with ferroelectric HfZrOx (FE-HZO) gate stack for the first time. Ion/Ioff ratios higher than 10 ⁷ and 10 ⁶ for p- and n-NWFETs, respectively, have been achieved by adopting the gate-all-around (GAA) configuration. Electrical biasing effects on the HZO ferroelectric reliability have been systematically investigated in this work. It is found that the polarization behavior will degrade with electrical stress time and can be recovered. The Ge HZO FinFET CMOS inverter shows experimentally voltage gain of 24.8 V/V.

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Title: Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability
Translated title: Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability
Creators - without role: C.-J. Su - National Institutes of Applied Research
T.-C. Hong - National Yang Ming Chiao Tung University
Y.-C. Tsou - National Cheng Kung University
F.-J. Hou - National Institutes of Applied Research
P.-J. Sung - National Institutes of Applied Research
M.-S. Yeh - National Institutes of Applied Research
C.-C. Wan - National Yang Ming Chiao Tung University
K.-H. Kao - National Cheng Kung University
Y.-T. Tang - National Institutes of Applied Research
C.-H. Chiu - National Yang Ming Chiao Tung University
C.-J. Wang - National Institutes of Applied Research
S.-T. Chung - National Yang Ming Chiao Tung University
T.-Y. You - National Institutes of Applied Research
Y.-C. Huang - National Institutes of Applied Research
C.-T. Wu - National Institutes of Applied Research
K.-L. Lin - Nano Hydrophobics (United States)
G.-L. Luo - National Institutes of Applied Research
K.-P. Huang - Industrial Technology Research Institute
Y.-J. Lee - National Institutes of Applied Research
T.-S. Chao - National Yang Ming Chiao Tung University
W.-F. Wu - National Institutes of Applied Research
G.-W. Huang - National Institutes of Applied Research
J.-M. Shieh - National Institutes of Applied Research
W.-K. Yeh - National Institutes of Applied Research
Y.-H. Wang - National Institutes of Applied Research
Publication Details: Technical Digest - International Electron Devices Meeting, IEDM, pp.15.4.1-15.4.4
Identifiers: 9781538635599; 9957772696806774
Academic Unit: Department of Engineering and System Science, College of Nuclear Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

Ge nanowire FETs with HfZrOx ferroelectric gate stack exhibiting SS of sub-60 mV/dec and biasing effects on ferroelectric reliability

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