Abstract
In this paper, we introduce a new graph partitioning problem that stems from a multiple-chip design style in which there is a chip library of chips containing predesigned circuit components (e.g. adders, multipliers etc) which are frequently used. Given an arbitrary circuit data flow graph, we have to realize the circuit by appropriately choosing a set of chips from the chip library. In selecting chips from the chip library to realize a given circuit, both the number of chips used and the interconnection cost are to be minimized. Our new graph partitioning problem models this chip selection problem. We present an efficient solution to this problem.