Abstract
This paper presents several optimization techniques of H.264/AVC decoder implementation on a dual-core VLIW PAC DSP platform. The evaluation results show that a video with D1 resolution can be decoded in real-time.
- Title
- H.264 Decoder Optimization – VLIW DSP Platform
- Creators - without role
- Pou-Hang IanJia-Ming ChenHsin-Wen WeiJian-Liang LuoWei-Kuan Shih - 國立清華大學電機資訊學院資訊工程學系
- Publication Details
- 18th VLSI Design/CAD Symposium,, p.104
- Identifiers
- 9957776044806774
- Academic Unit
- Department of Computer Science, College of Electrical Engineering and Computer Science, National Tsing Hua University
- Language
- Traditional Chinese
- Resource Type
- Conference paper