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HEVC interpolation filter architecture for quad full HD decoding
Conference paper

HEVC interpolation filter architecture for quad full HD decoding

Chao-Tsung Huang, Chiraag Juvekar, Mehul Tikekar and Anantha P. Chandrakasan
IEEE VCIP 2013 - 2013 IEEE International Conference on Visual Communications and Image Processing, 6706371
2013

Abstract

HEVC Interpolation filter VLSI
In this paper, an area-efficient and high-throughput interpolation filter architecture is presented for the latest video coding standard, High Efficiency Video Coding. A unified filter design is first proposed for the 8-tap luma and 4-tap chroma filters to optimize area, which uses only 13 adders. And a 2D filter architecture is then devised with an adaptive scheduling which supports all symmetric prediction partitions with a throughput of at least two samples/cycle. Experimental results also show that this architecture can achieve 2.58 samples/cycle on the average. The total gate count is 45.2k when synthesized at 200MHz with 40nm process, and the corresponding performance can support at least 3840×2160 videos at 30 fps. © 2013 IEEE.

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