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High Performance WSe                         2                          Transistors with Multilayer Graphene Source/Drain
Conference paper

High Performance WSe 2 Transistors with Multilayer Graphene Source/Drain

Chenhsin Lien, Hao-Ling Tang, Ming-Hui Chiu, Kuan-Jhih Hou, Shih-Hsien Yang, Jhih-Fong Su, Yen-Fu Lin and Lain-Jong Li
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings, 8565030
12/2018

Abstract

Graphene raised source/drain WSe 2 Electrical and Electronic Engineering
P-channel WSe FETs along with multilayer graphene source/drain (S/D) are demonstrated by the CVD growth of the WSe monolayer to the patterned graphene. Multilayer graphene (MLG) is adopted to reduce contact resistance while the monolayer WSe served as the channel for the electrostatics integrity of the FET. Furthermore, by increasing the p-type doping concentration of the graphene S/D, the I /I ratio can be enhanced to 10 and the unipolar p-channel characteristics are retained regardless the choice of the work function of the metal used for the S/D contact.

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