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High-RA STT-MRAM for In-Memory Computing: From Device Engineering to Prototype-IMC Validation
會議論文

High-RA STT-MRAM for In-Memory Computing: From Device Engineering to Prototype-IMC Validation

Ming-Chun Hong, Hsin-Han Lee, Guan-Long Chen, Sin-You Huang, Chiao-Yun Lo, Yi-Hui Su, Ho-Lin Tsai, Shih-Ching Chiu, Cheng-Yi Shih, Yao-Jen Chang, …
2026 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), 頁碼.1-2
IEEE
2026 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2026 - Proceedings of Technical Papers
2026
DOI: https://doi.org/10.1109/VLSITSA69131.2026.11527860

摘要

Arrays Cells (biology) Displays In-memory computing Indexes Indexing Magnesium Magnesium oxide Printing Very large scale integration
In contrast to the low-RA STT-MRAM for memory applications, high-RA (> 500 Ω*μm 2 ) STT-MRAM with high cell resistance (> 250 kΩ) is developed to support future energy-efficient in-memory computing (IMC). Scaling coercive magnetic field and cell dimensions together with the increase of MgO thickness are critical for enlarging RA and write margin. Unlike SOT-MRAM, IMC based on the high-RA STT-MRAM achieves high energy efficiency, excellent reliability, and robust immunity to variability and circuit non-ideality without compromising the advantage in density and technology maturity.

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