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High performance dual-gate ISFET with non-ideal effect reduction schemes in a SOI-CMOS bioelectrical SoC
Conference paper

High performance dual-gate ISFET with non-ideal effect reduction schemes in a SOI-CMOS bioelectrical SoC

Y.-J. Huang, C.-C. Lin, J.-C. Huang, C.-H. Hsieh, C.-H. Wen, T.-T. Chen, L.-S. Jeng, C.-K. Yang, J.-H. Yang, F. Tsui, …
Technical Digest - International Electron Devices Meeting, IEDM, Vol.2016-February, pp.29.2.1-29.2.4
16/02/2016

Abstract

A dual-gate ion-sensitive field-effect transistor (DGFET) with the back-side sensing structure implemented in a 0.18 μm SOI-CMOS SoC platform realizing high performance bioelectrical detection with non-ideal effect reduction is presented. Non-ideal effects of the conventional ISFET, such as time drift and hysteresis, are suppressed by the innovative scheme in DGFET using the bottom poly-gate (PG) transistor instead of the fluidic gate (FG) transistor for sensing. As a result, the signal-to-noise ratio (SNR) is improved by 155x, time drift is reduced by 53x, and hysteresis is reduced by 3.7x. For certain applications which require high sensitivity, a pulse-modulated biasing technique can be adopted to effectively reduce time drift with high pH sensitivity of 453 mV/pH which is ∼7.5x enhancement over the Nernst limit in the proposed DGFET.

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