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High-performance pMOSFETs with high-k gate dielectric and dislocation-free epitaxial Si/Ge super-lattice channel
Conference paper

High-performance pMOSFETs with high-k gate dielectric and dislocation-free epitaxial Si/Ge super-lattice channel

Li-Jung Liu, Kuei-Shu Chang-Liao, Chung-Hao Fu, Hsiao-Chi Hsieh, Chun-Chang Lu, Tien-Ko Wang, P.Y. Gu and M.J. Tsai
2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012, 6243324
2012

Abstract

The pMOSFET device with a novel Si/Ge super-lattice (SL) channel is proposed in this work. Experimental results show that the electrical characteristics can be obviously improved by SL virtual substrate. The peak hole mobility of pMOSFET device with SL is enhanced to twice as high as that with Si one. The on-off ratio of Id-Vg curve is beyond 8 orders, and the EOT value of gate dielectric can be ∼ 1 nm. The source/drain activation temperature at 650°C is especially suitable for high-k gate dielectric process. © 2012 IEEE.

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