High-speed C-testable systolic array design for Galois-Field inversion

Chih-Tsun Huang; Cheng-Wen Wu

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Conference paper

High-speed C-testable systolic array design for Galois-Field inversion

Chih-Tsun Huang and Cheng-Wen Wu

Proceedings of European Design and Test Conference, pp.342-346

1997

Abstract

Hardware and Architecture

Electrical and Electronic Engineering

Systolic architectures for inversion in Galois field (GF(2 ^m )) are presented. The proposed inversion algorithm is a counter-free extended Euclidean algorithm, which results in simple circuit implementation for GF inversion. Additionally, the bit-parallel implementation proposed is shown to be C-testable. Testability and modularity make it suited to VLSI implementation.

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Title: High-speed C-testable systolic array design for Galois-Field inversion
Translated title: High-speed C-testable systolic array design for Galois-Field inversion
Creators - without role: Chih-Tsun Huang - Natl Tsing Hua Univ
Cheng-Wen Wu - Natl Tsing Hua Univ
Publication Details: Proceedings of European Design and Test Conference, pp.342-346
Identifiers: 9957768133806774
Academic Unit: Department of Computer Science, College of Electrical Engineering and Computer Science, National Tsing Hua University; College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

High-speed C-testable systolic array design for Galois-Field inversion

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