High-speed C-testable systolic array design for galois-field inversion

Chih-Tsun Huang; Cheng-Wen Wu

Back

Conference paper

High-speed C-testable systolic array design for galois-field inversion

Chih-Tsun Huang and Cheng-Wen Wu

Proceedings of the 1997 European Conference on Design and Test, EDTC 1997, pp.342-346

03/1997

Abstract

Control and Systems Engineering

Computer Science (all)

Systolic architectures for inversion in Galois field (GF(2m)) are presented. The proposed inversion algorithm is a counter-free extended Euclidean algorithm, which results in simple circuit implementation for GF inversion. Additionally, the bit-parallel implementation proposed is shown to be C-testable. Testability and modularity make it suited to VLSI implementation.

Metrics

1 Record Views

Details

Title: High-speed C-testable systolic array design for galois-field inversion
Creators - without role: Chih-Tsun Huang - Department of Electrical Engineering , National Tsing Hua University
Cheng-Wen Wu - National Tsing Hua University
Identifiers: 0818677864; 9780818677861; 9957775239506774
Academic Unit: Department of Computer Science, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper
Publication Details: Proceedings of the 1997 European Conference on Design and Test, EDTC 1997, pp.342-346

High-speed C-testable systolic array design for galois-field inversion

Abstract

Related links

Metrics

Details

National Tsing Hua University Social media