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High voltage lateral 4H-SiC JFETs on a semi-insulating substrate
Conference paper

High voltage lateral 4H-SiC JFETs on a semi-insulating substrate

Chih-Fang Huang, Cheng-Li Kan, Tian-Li Wu, Meng-Chia Lee, Yo-Zthu Liu, Kung-Yen Lee and Feng Zhao
Device Research Conference - Conference Digest, DRC, pp.275-276
11/12/2009

Abstract

Because of the superior material properties, silicon carbide (SiC) devices have drawn considerable attention in high power and high temperature applications. Promising performance has been demonstrated on both vertical and lateral devices [1] - [3]. In this paper, we report the performance of high voltage lateral 4H-SiC JFETs built on a semi-insulating substrate. The drift region design is based on charge compensation of the n-and p-type materials. The best achieved breakdown voltage is 3510 V, which is the highest value ever published for SiC lateral switching devices. R on, sp is 390 mΩ-cm 2 , resulting in a BV 2 /R on, sp of 32 MW/cm 2 . © 2009 IEEE.

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