Abstract
A high voltage tolerant (HVT) electro-static-discharge (ESD) design was proposed for analog applications in deep submicron CMOS technologies. The design, which adopted one forward biased P+/N-Well diode in series of one stacked NMOS, reduced the total capacitance and maintained high ESD performance. The performance of the ESD design in protecting the 3.3 V and 1.8 V CMOS devices was HBM 6 KV/MM 550 V and HBM 4 KV/MM 350 V respectively.