Abstract
Two-dimensional electronics based on single-layer (SL) MoS 2 offers significant advantages for realizing large-scale flexible systems owing to the ultrathin nature, good transport properties and stable crystalline structure of MoS 2 . However, the reported devices and circuits based on this material have low yield because of various variation sources inherent to the growth and fabrication technology. In this work, we develop a variation-aware design flow and yield model to evaluate the MoS 2 technology and provide a guideline for the co-optimization of the material, devices and circuits. Test chips with various inverters and basic logic gates (such as NAND and XOR) are fabricated as demonstration of the close-to-unit yield of the proposed technology platform.