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II-gate nanowires TANOS poly-Si TFT nonvolatile memory
Conference paper

II-gate nanowires TANOS poly-Si TFT nonvolatile memory

Min-Feng Hung, Jiang-Hung Chen and Yung-Chun Wu
2010 Silicon Nanoelectronics Workshop, SNW 2010, 5562547
2010

Abstract

This work we demonstrate a TANOS nonvolatile memory (NVM) with poly-Si nanowire (NW) channels and Pi-gate (π-gate) structure. π-gate structure in this TANOS NVM increase on current (I on ), decrease threshold voltage (V th ) and subthreshold slope (SS), and enlarge the memory window (δV th ). This NVM device behaves fast program/erase (P/E) speed; 3 V memory window can be achieved by applying 18 V in 10 μs. The 70 % of initial memory window has been maintained after 10 4 P/E-cycle stress.

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