Abstract
E-beam maskless lithography is a potential solution for 32-nm half-pitch (HP) node and beyond. The major concern to implement it for mass production is whether its throughput can reach a production-worthy level. Without violating the law of physics using unrealistic e-beam current, parallelisms in the writing beams and the data path are a few possible solutions to achieve such high productivity. It has been proposed to realize throughput greater than 10 wafers per hour (WPH) from a single column with >10,000 e-beams writing in parallel, or even greater than 100 WPH by further clustering multiple columns within an acceptable tool footprint. The MAPPER concept contains a CMOS-MEMS blanker array supported by high-speed optical data-path architecture to simultaneously control this high number of beams, switching them on and off independently. The MAPPER pre-α tool with a 110-beam 5-keV column and a 300-mm wafer stage has been built and is ready for imaging test. In this paper, the resist imaging results of 110-beam parallel raster-scan writing for 32-nm logic circuit layout on 300-mm wafer is shown. The challenges of implementing multiple e-beam maskless lithography (MEBML2) in mass production environment, including illumination, focusing, and CD uniformity, are discussed. © 2009 Copyright SPIE - The International Society for Optical Engineering.