Abstract
A properly designed HV-VDMOSFET (High-voltage Vertical Double-diffusion Metal Oxide Semiconductor Field Effect Transistor) must pass reliability tests such as the HTRB (High Temperature Reverse Bias) test before they can be delivered to the customer. To reduce costs, the possibility of shrinking the transition region between the active cells and the edge termination, as well as eliminating the passivation and its related mask layer, is usually considered. In this study, we show that an HV-VDMOS will experience a Vth drop and an IDSS leakage current after HTRB stress. However, with the assistance of TCAD (Silvaco) simulation in combination with experiment results based on different process splits, the root causes are identified and a solution is proposed and verified.