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Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via
Conference paper

Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via

Srivatsa Rangachar Srinivasa, Karthik Mohan, Wei-Hao Chen, Kuo-Hsinag Hsu, Xueqing Li, Meng-Fan Chang, Sumeet Kumar Gupta, John Sampson and Vijaykrishnan Narayanan
Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, Vol.2017-July, pp.128-133
07/2017

Abstract

monolithic 3D integration reconfigurability switch box vertical via Hardware and Architecture Control and Systems Engineering Electrical and Electronic Engineering
This paper proposes to use the high density of vias enabled by monolithic 3D integration to produce multi-stack FPGA designs with improved performance and functionality. The use of fine grain vertical interconnects enables reconfiguration of FPGA logic within a few clock cycles, as shown in our design that features dynamic reconfiguration capabilities through the use of a pair of configuration memories on the upper stack. Along with the reconfigurability feature, results show that our SLICE design offers an area reduction of 23% compared to a standard design without reconfiguration capability. Our analysis of FPGA switch box logic and physical design with M3D vias provides insights into the sources of benefits from vertical routing in a multi-stacked design. We also discuss the design overheads involved in incorporating multiple inter-stack vias for better and faster communication among logic routed in different design stacks.

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