Abstract
Design verification has become a bottleneck of modern designs. Recently, simulation-based random verification has attracted a lot of interests due to its effectiveness in uncovering obscure bugs. Designers are often required to provide the input probabilities while conducting the random verification. However, it is extremely difficult for designers to provide accurate input probabilities. In this paper, we propose an iterative algorithm that derives good input probabilities so that the design intent can be exercised effectively for functional verification. We conduct extensive experiments on both benchmark circuit and industrial designs. The experimental results are very promising. © 2007 IEEE.