Abstract
Video coding is essential to many applications such as MPEG-1 for VCD, MPEG-2 for DVD and DTV, and MPEG-4 for Video Over IP Network. Ever increasing semiconductor capacity makes possible more advanced coding methods that achieve better coding efficiency at the expense of more computation. H.264/AVC is the latest video coding standard jointly developed by ITU and MPEG Committee [5]. Since its introduction two years ago, we have observed intensive research and development activity worldwide. Many approaches have been proposed for various H.264/AVC-based applications. They range from pure software implementation in CPU or DSP, multi-processor, Application-Specific Instruction-set Processor (ASIP), Co-processor to pure hardwired accelerator. For low power portable or very high-end applications, a hardwired coding/decoding engine is preferred. Since software portion is indispensable to support additional features such as error resilience and rate control, the hardware engine should be equipped with standard bus interface so that it can be integrated into embedded systems with different types of CPUs. Notable hardware accelerators in the open literature include NCTU [2], NTU [3], Conexant [4] and CCU [1]. Few previous works have considered system-level overhead resulting from communicating with various components such as storage devices, SDRAM, display controller, and CPU. In this paper, we analyze the whole system performance and optimize two main bottlenecks: system bus bandwidth and decoder accelerator throughput.