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Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication
Conference paper

Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication

Wei-Yuan Chang, Chun-Lin Chu, Guang-Li Luo, Yi-Shuo Huang, Chun-Hsiung Lin, Po-Jung Sung, Yao-Jen Lee, Shih-Hong Chen, Bo-Yuan Chen, Wen-Fa Wu, …
2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022
2022
DOI: https://doi.org/10.1109/VLSI-TSA54299.2022.9770996

Abstract

Electronic Optical and Magnetic Materials Computer Science Applications Hardware and Architecture Electrical and Electronic Engineering Safety Risk Reliability and Quality
The Si0.8Ge0.2 GAA-FET were successfully fabricated with Si GAA-FET using the same epi-layers and HKMG process for CMOS device fabrication. This study approached two selective etching processes and investigated both etched surfaces to obtain the multi-bridge channels (MBCs) for advanced SiGe p-FET and Si n-FET. The etched Si layers used in GAAFETs showed a practical on/off ratio with a subthreshold slope (SS) of 90 mV/decade. On the other hand, the etched surface of the advanced SiGe layers showed noticeable interface defects, and it was optimized by using PMA 800oC/5min.

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