Abstract
This paper proposes a low-cost cell-based solution for the jitter measurement of a given clock signal. We developed a tiny Cyclic Time-to-Digital Converter (Cyclic-TDC) to achieve this purpose. Our Cyclic- TDC has a flexible range that adapts to the frequency of the input clock signal. Furthermore, we identify the source of the measurement uncertainty and optimize it with a simple yet effective just-enough strategy. The proposed method is especially easy to use as it consists of only standard cells. Experimental results will demonstrate that we can reduce the measurement uncertainty by 57% and 52% for two clock signals, respectively when implemented in a 90nm CMOS process.