Abstract
Clock skew optimization is a complicated problem in modern VLSI technologies because circuits often operate in many environments (corners) such as different power supply voltage and temperature or functional modes (modes) like voltage modes. While circuits operate in different corners or modes, cell delay varies a lot. It will lead to large skew variation. Therefore, to optimize clock skew in all corners or modes is very important. In this paper, we develop an approach to minimize clock skew considering multi-corner multi-mode conditions. Our experimental results shows there are 10.3% improvement compared with the commercial tool SOC Encounter. ©2010 IEEE.