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Leveraging data lifetime for energy-Aware last level non-volatile sram caches using redundant store elimination
Conference paper

Leveraging data lifetime for energy-Aware last level non-volatile sram caches using redundant store elimination

Hsiang-Jen Tsai, Chien-Chih Chen, Keng-Hao Yang, Ting-Chin Yang, Li-Yue Huang, Ching-Hao Chung, Meng-Fan Chang and Tien-Fu Chen
Proceedings - Design Automation Conference, 2593153
2014

Abstract

Energy reduction Memory structure Multi-core Non-volatile SRAM Nonvolatile memory On-chip cache architecture Redundant store elimination
NVM has commonly been used to address increasingly large last-level caches (LLCs) requirements by reducing leakage. However, frequent data-writing operations result in increased energy consumption. In this context, a promising memory technology, Non-volatile SRAM (nvSRAM), enables normal and standby operation modes which can be used to store various types of data. However, nvSRAM suffers from high dynamic energy usage due to frequent switching between operation modes. In this paper, we propose a redundant store elimination (RSE) scheme which, on average, discards 94% of needless bitwrite operations. Moreover, we present a retention-Aware cache management policy to reduce data updates of cache blocks, based on the correlation between data lifetime and cache types. Experimental results demonstrate that our proposal can improve energy consumption of SRAM-based and RRAM-based LLCs by 57% and 31%, respectively. Copyright 2014 ACM.

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