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Logarithmic CMOS image sensor through multi-resolution analog-to-digital conversion
Conference paper

Logarithmic CMOS image sensor through multi-resolution analog-to-digital conversion

Shih-Fang Chen, Ying-Jie Juang, Shi-Yu Huang and Ya-Chin King
International Symposium on VLSI Technology, Systems, and Applications, Proceedings, Vol.2003-January, pp.227-230
2003

Abstract

In this paper we present a CMOS image sensor design with a better sensitivity to low light intensity. This feature is achieved through a multi-resolution analog-to-digital converter (ADC). By doing so, the opto-electrical characteristic of a sensor cell can be finely tuned. A costeffective architecture for realizing the required ADC is also proposed. This architecture leads to a faster conversion time as well as a smaller area. A simulation environment with post-layout accuracy is incorporated to demonstrate the advantages. It shows that a number of images can be captured more clearly than a traditional sensor. © 2003 IEEE.

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