Abstract
The main obstacle in testing CMOS stuck-on faults is that the test vectors must be applied relatively slowly for static current monitoring to be carried out reliably. As to stuck-open faults, they can create unintended states such that test generation is greatly complicated. In this paper, we propose a design for testability (DFT) approach to detect stuck-on and stuck-open faults using voltage (logic-level) monitoring instead of current monitoring. The area overhead and performance penalty is small.